1. Field of the Invention
The present invention relates to the field of computer designs with one or more processors coupled by a bus for signaling.
2. Description of Related Art
Traditional computer designs typically incorporate one or more general-purpose programmable processors, and a variety of specialized processors whose capabilities are restricted to specific functions. Specialized processors conserve general-purpose processor resources by performing specific functions generalized processors would otherwise be required to perform.
An example of a specialized processor in the prior art is an interrupt controller that prioritizes and presents a plurality of interrupt requests to a general-purpose processor. General-purpose processors often select the precise scheme their interrupt controllers use by presenting configuration information to the interrupt controller's Input/Output ports. Therefore, the general-purpose processor programs the interrupt controller's processing behavior such as presenting interrupts on a strict priority or round-robin basis. In the most fundamental sense, such interrupt controllers represent specialized processors whose functions are restricted to specific programmable functions.
In addition to a multiplicity of specialized processors, computer system architects increasingly incorporate multiple general-purpose processors in their designs. This helps escape processing limitations of a single general-purpose processor. One way additional general-purpose processors are included is through a design's provision for intelligent adapter cards. Intelligent adapter cards may contain both general-purpose adapter processors and specialized processors that collect or manipulate data before passing it to a general-purpose processor.
Alternately, computer system architects may include multiple general-purpose processors that collectively process information. Finally, computer system architects may include both multiple general-purpose processors and intelligent adapter cards in a design.
In any of these approaches, architects necessarily include provisions for synchronizing the various processors. Specifically, architects must pay particular attention to the mechanisms a plurality of processors use to synchronize and communicate activities. As an example, multiple processors that share a common data memory must detect when other processors change data values stored in the memory. This allows processors to invalidate their caches, causing a subsequent cache refresh for the data item's changed value when it is needed. Cache updates occur at a hardware level and are transparent to a processor's software. Such hardware cache-coherency considerations are well documented in John L. Hennessy's and David A. Patterson's Computer Architecture A Quantitative Approach published by Morgan Kaufmann Publishers Inc., 1990.
Other multi-processor synchronization and communication techniques involve semaphores and work queues. Since both the semaphore and queue approaches require a shared memory, they are hereafter collectively considered as shared address space control structures. Software manipulation of shared address space control structures are well known and representative of multi-processor synchronization state-of-the-art despite their potential to present significant performance problems. In such approaches, shared address space control structures reside at agreed-upon, known addresses and processors manipulate them under software control. It is desirable that when processors access these structures, other processors learn of the access selectively in a non-disruptive manner though this is often difficult if not impossible under software control.
Computer designers currently approach independent processor signaling with a variety of well known and understood software approaches. However, these approaches are not efficient, and unnecessarily consume precious processor resources. Non-disruptive hardware signaling is largely restricted to cache coherency applications.
Techniques that improve processor-to-processor communication efficiency are of great commercial importance because they allow lower-cost processors and components to perform work that previously required the use of higher-cost processors and components. Increased efficiency, therefore, leads directly to computer system designs that have lower costs, improved performance, or both. Thus, there is a need for a system and a method to improve processor-to-processor communication and signaling.